View NCV898031_4729462.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2012 june, 2012 ? rev. 1 1 publication order number: NCV898031/d NCV898031 2 mhz non-synchronous sepic/boost controller the NCV898031 is an adjustable output non ? synchronous 2 mhz sepic/boost controller which drives an external n ? channel mosfet. the device uses peak current mode control with internal slope compensation. the ic incorporates an internal regulator that supplies charge to the gate driver. protection features include internally ? set soft ? start, undervoltage lockout, cycle ? by ? cycle current limiting and thermal shutdown. additional features include low quiescent current sleep mode and microprocessor compatible enable pin. features ? peak current mode control with internal slope compensation ? 1.2 v 2% reference voltage ? 2 mhz fixed frequency operation ? wide input voltage range of 3.2 v to 40 v, 45 v load dump ? input undervoltage lockout (uvlo) ? internal soft ? start ? low quiescent current in sleep mode (< 10 a typical) ? cycle ? by ? cycle current limit protection ? hiccup ? mode overcurrent protection (ocp) ? hiccup ? mode short ? circuit protection (scp) ? thermal shutdown (tsd) ? this is a pb ? free device typical applications ? small form factor point ? of ? load power regulation ? headlamps ? backlighting marking diagram http://onsemi.com soic ? 8 d suffix case 751 1 8 pin connections 1 8 2 3 4 7 6 5 (top view) en isns gnd gdrv vfb vc vin vdrv 898031 = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free package 898031 alyw 1 8 device package shipping ? ordering information NCV898031d1r2g soic ? 8 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
NCV898031 http://onsemi.com 2 gm csa l1 sc clk enable en vc pwn r c c c r sns r f1 v ref c drv v g v o c g c o figure 1. simplified block diagram and application schematic 8 3 2 4 6 gnd isns gdrv vin vfb 5 vdrv osc q d temp vdrv drive logic cl scp ss fault logic 1 7 + l2 c cpl r f2 package pin descriptions pin no. pin symbol function 1 en enable input. the part is disabled into sleep mode when this pin is brought low for longer than the enable time ? out period. 2 isns current sense input. connect this pin to the source of the external n ? mosfet, through a current ? sense resistor to ground to sense the switching current for regulation and current limiting. 3 gnd ground reference. 4 gdrv gate driver output. connect to gate of the external n ? mosfet. a series resistance can be added from gdrv to the gate to tailor emc performance. 5 vdrv driving voltage. internally ? regulated supply for driving the external n ? mosfet, sourced from vin. bypass with a 1.0 f ceramic capacitor to ground. 6 vin input voltage. if bootstrapping operation is desired, connect a diode from the input supply to vin, in addi- tion to a diode from the output voltage to vdrv and/or vin. 7 vc output of the voltage error amplifier. an external compensator network from vc to gnd is used to stabilize the converter. 8 vfb output voltage feedback. a resistor from the output voltage to vfb with another resistor from vfb to gnd creates a voltage divider for regulation and programming of the output voltage.
NCV898031 http://onsemi.com 3 absolute maximum ratings (voltages are with respect to gnd, unless otherwise indicated) rating value unit dc supply voltage (vin) ? 0.3 to 40 v peak transient voltage (load dump on vin) 45 v dc supply voltage (vdrv, gdrv) 12 v peak transient voltage (vfb) ? 0.3 to 6 v dc voltage (vc, vfb, isns) ? 0.3 to 3.6 v dc voltage (en) ? 0.3 to 6 v dc voltage stress (vin ? vdrv)* ? 0.7 to 40 v operating junction temperature ? 40 to 150 c storage temperature range ? 65 to 150 c peak reflow soldering temperature: pb ? free, 60 to 150 seconds at 217 c 265 peak c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. *an external diode from the input to the vin pin is required if bootstrapping vdrv and vin off of the output voltage. package capabilities characteristic value unit esd capability (all pins) human body model machine model 2.0 200 kv v moisture sensitivity level 1 package thermal resistance junction ? to ? ambient, r ja (note 1) 100 c/w 1. value based on copper are of 650 mm 2 (or 1 in 2 ) of 1 oz copper thickness and fr4 pcb substrate.
NCV898031 http://onsemi.com 4 electrical characteristics ( ? 40 c < t j < 150 c, 3.2 v < v in < 40 v, unless otherwise specified) min/max values are guaranteed by test, design or statistical correlation. characteristic symbol conditions min typ max unit general quiescent current, sleep mode i q,sleep v in = 13.2 v, en = 0, t j = 25 c ? 2.0 ? a quiescent current, sleep mode i q,sleep v in = 13.2 v, en = 0, ? 40 c < t j < 125 c ? 2.0 6.0 a quiescent current, no switching i q,off into vin pin, en = 1, no switching ? 1.5 2.5 ma quiescent current, switching, normal operation i q,on into vin pin, en = 1, switching ? 4.0 6.0 ma oscillator minimum pulse width t on,min 30 65 90 ns maximum duty cycle d max 85 88 90 % switching frequency f s 1.8 2.0 2.2 mhz soft ? start time t ss from start of switching with v fb = 0 until reference voltage = v ref 520 650 780 s soft ? start delay t ss,dly from en 1 until start of switching with v fb = 0 80 100 280 s slope compensating ramp s a 28 34 40 mv/ s enable en pull ? down current i en v en = 5 v ? 5.0 10 a en input high voltage v s,ih 2.0 ? 5.0 v en input low voltage v s,il 0 ? 800 mv en time ? out ratio %t en from en falling edge, to oscillator control (en high) or shutdown (en low), percent of typical switching frequency ? 250 350 % current sense amplifier low ? frequency gain a csa input ? to ? output gain at dc, isns 1 v 0.9 1.0 1.1 v/v bandwidth bw csa gain of a csa ? 3 db 2.5 ? ? mhz isns input bias current i sns,bias out of isns pin ? 30 50 a current limit threshold voltage v cl voltage on isns pin 360 400 440 mv current limit, response time t cl cl tripped until gdrv falling edge, v isns = v cl + 40 mv ? 80 125 ns overcurrent protection, threshold voltage %v ocp percent of v cl 125 150 175 % overcurrent protection, response time t ocp from overcurrent event, until switching stops, v isns = v ocp + 40 mv ? 80 125 ns voltage error operational transconductance amplifier transconductance g m,vea v fb ? v ref = 20 mv 0.92 1.28 1.63 ms vea output resistance r o,vea 2.0 ? ? m vfb input bias current i vfb,bias current out of vfb pin ? 0.5 2.0 a reference voltage v ref 1.176 1.200 1.224 v vea maximum output voltage v c,max 2.5 ? ? v vea minimum output voltage v c,min ? ? 0.3 v vea sourcing current i src,vea vea output current, vc = 2.0 v 80 100 ? a vea sinking current i snk,vea vea output current, vc = 0.7 v 80 100 ? a
NCV898031 http://onsemi.com 5 electrical characteristics ( ? 40 c < t j < 150 c, 3.2 v < v in < 40 v, unless otherwise specified) min/max values are guaranteed by test, design or statistical correlation. characteristic unit max typ min conditions symbol gate driver sourcing current i src v drv 6 v, v drv ? v gdrv = 2 v 600 800 ? ma sinking current i sink v gdrv 2 v 500 600 ? ma driving voltage dropout v drv,do v in ? v drv , iv drv = 25 ma ? 0.3 0.6 v driving voltage source current i drv v in ? v drv = 1 v 35 45 ? ma backdrive diode voltage drop v d,bd v drv ? v in , i d,bd = 5 ma ? ? 0.7 v driving voltage v drv i vdrv = 0.1 ? 25 ma 6.0 6.3 6.6 v uvlo undervoltage lock ? out, threshold voltage v uvlo v in falling 2.95 3.05 3.15 v undervoltage lock ? out, hysteresis v uvlo,hys v in rising 50 150 250 mv thermal shutdown thermal shutdown threshold t sd t j rising 160 170 180 c thermal shutdown hysteresis t sd,hys t j falling 10 15 20 c thermal shutdown delay t sd,dly from t j > t sd to stop switching ? ? 100 ns
NCV898031 http://onsemi.com 6 typical performance characteristics 010203040 v in , input voltage (v) figure 2. sleep current vs. input voltage i q,sleep , sleep current ( a) t j = 25 c figure 3. sleep current vs. temperature ? 50 50 100 150 200 t j , junction temperature ( c) figure 4. quiescent current vs. temperature t on,min minimum on time (ns) t j , junction temperature ( c) figure 5. minimum on time vs. temperature ? 50 0 50 100 200 t j , junction temperature ( c) figure 6. normalized current limit vs. temperature ? 40 10 60 110 160 normalized current limit (25 c) i q,on , quiescentcurrent (ma) figure 7. reference voltage vs. temperature ? 50 0 50 100 200 i q,sleep , sleep current ( a) v in = 13.2 v 0 1 2 3 4 5 6 150 t j , junction temperature ( c) 0 1 2 3 4 5 7 6 4.76 4.78 4.82 4.84 4.86 4.88 4.92 0.990 0.995 1.000 1.005 1.010 61.5 62.0 62.5 63.0 64.5 64.0 0 1.195 1.197 1.199 1.201 1.203 1.205 t j , junction temperature ( c) v ref , reference voltage (v) ? 40 10 60 110 160 v in = 13.2 v 4.80 4.90 150 63.5
NCV898031 http://onsemi.com 7 typical performance characteristics figure 8. enable pulldown current vs. voltage t j , junction temperature ( c) figure 9. enable pulldown current vs. temperature i enable , pulldown current ( a) 01234 v enable , voltage (v) i enable , pulldown current ( a) t j = 25 c 56 ? 40 10 60 110 160 0 1 2 3 4 5 7 6 5.0 5.5 6.0 6.5 7.0 7.5 8.0 current mode control the NCV898031 incorporates a current mode control scheme, in which the pwm ramp signal is derived from the power switch current. this ramp signal is compared to the output of the error amplifier to control the on ? time of the power switch. the oscillator is used as a fixed ? frequency clock to ensure a constant operational frequency. the resulting control scheme features several advantages over conventional voltage mode control. first, derived directly from the inductor, the ramp signal responds immediately to line voltage changes. this eliminates the delay caused by the output filter and the error amplifier, which is commonly found in voltage mode controllers. the second benefit comes from inherent pulse ? by ? pulse current limiting by merely clamping the peak switching current. finally, since current mode commands an output current rather than voltage, the filter offers only a single pole to the feedback loop. this allows for a simpler compensation. the NCV898031 also includes a slope compensation scheme in which a fixed ramp generated by the oscillator is added to the current ramp. a proper slope rate is provided to improve circuit stability without sacrificing the advantages of current mode control. current limit the NCV898031 features two current limit protections, peak current mode and over current latch off. when the current sense amplifier detects a voltage above the peak current limit between isns and gnd after the current limit leading edge blanking time, the peak current limit causes the power switch to turn off for the remainder of the cycle. set the current limit with a resistor from isns to gnd, with r = v cl / i limit . if the voltage across the current sense resistor exceeds the over current threshold voltage, the device enters over current hiccup mode. the device will remain off for the hiccup time and then go through the soft ? start procedure. short circuit protection if the short circuit enable bit is set (sce = y), the device will attempt to protect the power mosfet from damage. when the output voltage falls below the short circuit trip voltage, after the initial short circuit blanking time, the device enters short circuit latch ? off. the device will remain off for the hiccup time and then go through the soft ? start. enable the enable pin has two modes. when a dc logic high (cmos/ttl compatible) voltage is applied to this pin, the NCV898031 operates at the programmed frequency. when a dc logic low voltage is applied, the NCV898031 enters a low quiescent current sleep mode. the NCV898031 requires 2 clock cycles after the falling edge of the enable signal to stop switching. uvlo input undervoltage lockout (uvlo) is provided to ensure that unexpected behavior does not occur when vin is too low to support the internal rails and power the controller. the ic will start up when enabled and vin surpasses the uvlo threshold plus the uvlo hysteresis and will shut down when vin drops below the uvlo threshold or the part is disabled.
NCV898031 http://onsemi.com 8 internal soft - start to insure moderate inrush current and reduce output overshoot, the NCV898031 features a soft start which charges a capacitor with a fixed current to ramp up the reference voltage. vdrv an internal regulator provides the drive voltage for the gate driver. bypass with a ceramic capacitor to ground to ensure fast turn on times. the capacitor should be between 0.1 f and 1 f, depending on switching speed and charge requirements of the external mosfet. oscillator slope compensation + q s r NCV898031 voltage error vea csa pwm comparator gate drive compensation gdrv l2 l1 figure 10. sepic current mode schematic v fb i sns v in r l c o c cpl sepic design methodology this section details an overview of the component selection process for the NCV898031 in continuous conduction mode sepic. it is intended to assist with the design process but does not remove all engineering design work. many of the equations make heavy use of the small ripple approximation. this process entails the following steps: 1. define operational parameters 2. select current sense resistor 3. select sepic inductors 4. select coupling capacitor 5. select output capacitors 6. select input capacitors 7. select feedback resistors 8. select compensator components 9. select mosfet(s) 10. select diode define operational parameters before beginning the design, define the operating parameters of the application. these include: v in(min) : minimum input voltage [v] v in(max): maximum input voltage [v] v out : output voltage [v] i out(max) : maximum output current [a] i cl : desired typical cycle ? by ? cycle current limit [a] from this the ideal minimum and maximum duty cycles can be calculated as follows: d min v out v in(max) v out d max v out v in(min) v out both duty cycles will actually be higher due to power loss in the conversion. the exact duty cycles will depend on conduction and switching losses. if the calculated d wc (worst case) is higher than the d max limit of the NCV898031, the conversion will not be possible. it is important for a sepic converter to have a restricted d max , because while the ideal conversion ratio of a sepic converter goes up to infinity as d approaches 1, a real converter?s conversion ratio starts to decrease as losses overtake the increased power transfer. if the converter is in this range it will not be able to regulate properly. if the following equation is not satisfied, the device will skip pulses at high v in : d min f s t on(min) where: f s : switching frequency [hz] t on(min) : minimum on time [s]
NCV898031 http://onsemi.com 9 select current sense resistor current sensing for peak current mode control and current limit relies on the mosfet current signal, which is measured with a ground referenced amplifier . note that the i cl equals the sum of the currents from both inductors. the easiest method of generating this signal is to use a current sense resistor from the source of the mosfet to device ground. the sense resistor should be selected as follows: r s v cl i cl where: r s : sense resistor [ ] v cl : current limit threshold voltage [v] i cl : desire current limit [a] select coupling inductors the output inductor controls the current ripple that occurs over a switching period. a high current ripple will result in excessive power loss and ripple current requirements. a low current ripple will result in a poor control signal and a slow current slew rate in case of load steps. a good starting point for peak to peak ripple is around 20 ? 40% of the inductor current at the maximum load at the worst case v in , but operation should be verified empirically. the worst case v in is half of v out , or whatever v in is closest to half of v in . after choosing a peak current ripple value, calculate the inductor value as follows: l v in(wc) 2 d wc i l,max f s v out where: v in(wc) : v in value as close as possible to half of v out [v] d wc : duty cycle at v in(wc) i l,max : maximum peak to peak ripple [a] the maximum average inductor current can be calculated as follows: i l1,avg v out i out(max) v in(wc) the peak inductor current can be calculated as follows: i l1,peak i l1,avg i l1 2 i l2,peak i out(max) i l2 2 where (if l1 = l2): i l1 = i l2 select coupling capacitor coupling capacitor rms current is significant. a low esr ceramic capacitor is required as a coupling capacitor. selecting a capacitor value too low will result in high capacitor ripple voltage which will distort ripple current and diminish input line regulation capability. budgeting 2 ? 5% coupling capacitor ripple voltage is a reasonable guideline. v coupling i out d wc c coupling f s current mode control helps resolve some of the resonant frequencies that create issues in voltage mode sepic converter designs, but some resonance issues may occur. a resonant frequency exists at f resonance 1 2 (l1 l2)c coupling it may become necessary to place an rc damping network in parallel with the coupling capacitor if the resonance is within ~1 decade of the closed ? loop crossover frequency. the capacitance of the damping capacitor should be ~5 times that of the coupling capacitor. the optimal damping resistance (including the esr of the damping capacitor) is calculated as r damping l1 l2 c coupling select output capacitors the output capacitors smooth the output voltage and reduce the overshoot and undershoot associated with line transients. the steady state output ripple associated with the output capacitors can be calculated as follows: v out(ripple) i out(max) d wc c out f s i out(max) 1 d wc d wc v in(min) 2 f s l 2
r esr the capacitors need to survive an rms ripple current as follows: i cout(rms) i out(max) 2 d wc i 2 a i 2 r 3 i a i r
d wc where i a i l1_peak i l2_peak i l1_peak i r i l1 i l2 the use of parallel ceramic bypass capacitors is strongly encouraged to help with the transient response. select input capacitors the input capacitor reduces voltage ripple on the input to the module associated with the ac component of the input current. i cin(rms) i l1 12 select feedback resistors the feedback resistors form a resistor divider from the output of the converter to ground, with a tap to the feedback pin. during regulation, the divided voltage will equal v ref . the lower feedback resistor can be chosen, and the upper feedback resistor value is calculated as follows: r upper r lower v out v ref
v ref
NCV898031 http://onsemi.com 10 the total feedback resistance (r upper + r lower ) should be in the range of 1 k ? 100 k . select compensator components current mode control method employed by the NCV898031 allows the use of a simple, type ii compensation to optimize the dynamic response according to system requirements. select mosfet(s) in order to ensure the gate drive voltage does not drop out the mosfet(s) chosen must not violate the following inequality: q g(total) i drv f s where: q g(total) : total gate charge of mosfet(s) [c] i drv : drive voltage current [a] f s : switching frequency [hz] the maximum rms current can be calculated as follows: i d(max) d wc i q(peak) 2 i l1 i l2
2 3 i q(peak) i l1 i l2

where i q(peak) i l1_peak i l2_peak the maximum voltage across the mosfet will be the maximum output voltage, which is the higher of the maximum input voltage and the regulated output voltaged: v q(max) v out(max) select diode the output diode rectifies the output current. the average current through diode will be equal to the output current: i d(avg) i out(max) additionally, the diode must block voltage equal to the higher of the output voltage and the maximum input voltage: v d(max) v out(max) the maximum power dissipation in the diode can be calculated as follows: p d v f (max) i out(max) where: p d : power dissipation in the diode [w] v f(max) : maximum forward voltage of the diode [v] oscillator slope compensation + NCV898031 voltage error vea csa pwm comparator gate drive compensation l gdrv figure 11. boost current mode schematic s r q c o r l v out v fb i sns v in
NCV898031 http://onsemi.com 11 boost topology application information design methodology this section details an overview of the component selection process for the NCV898031 in continuous conduction mode boost. it is intended to assist with the design process but does not remove all engineering design work. many of the equations make heavy use of the small ripple approximation. this process entails the following steps: 1. define operational parameters 2. select current sense resistor 3. select output inductor 4. select output capacitors 5. select input capacitors 6. select feedback resistors 7. select compensator components 8. select mosfet(s) 9. select diode define operational parameters before beginning the design, define the operating parameters of the application. these include: v in(min) : minimum input voltage [v] v in(max): maximum input voltage [v] v out : output voltage [v] i out(max) : maximum output current [a] i cl : desired typical cycle ? by ? cycle current limit [a] from this the ideal minimum and maximum duty cycles can be calculated as follows: d min 1 v in(max) v out d wc 1 v in(wc) v out both duty cycles will actually be higher due to power loss in the conversion. the exact duty cycles will depend on conduction and switching losses. if the maximum input voltage is higher than the output voltage, the minimum duty cycle will be negative. this is because a boost converter cannot have an output lower than the input. in situations where the input is higher than the output, the output will follow the input, minus the diode drop of the output diode and the converter will not attempt to switch. if the calculated d wc is higher than the d max limit of the NCV898031, the conversion will not be possible. it is important for a boost converter to have a restricted d max , because while the ideal conversion ratio of a boost converter goes up to infinity as d approaches 1, a real converter?s conversion ratio starts to decrease as losses overtake the increased power transfer. if the converter is in this range it will not be able to regulate properly. if the following equation is not satisfied, the device will skip pulses at high v in : d min f s t on(min) where: f s : switching frequency [hz] t on(min) : minimum on time [s] select current sense resistor current sensing for peak current mode control and current limit relies on the mosfet current signal, which is measured with a ground referenced amplifier. the easiest method of generating this signal is to use a current sense resistor from the source of the mosfet to device ground. the sense resistor should be selected as follows: r s v cl i cl where: r s : sense resistor [ ] v cl : current limit threshold voltage [v] i cl : desire current limit [a] select output inductor the output inductor controls the current ripple that occurs over a switching period. a high current ripple will result in excessive power loss and ripple current requirements. a low current ripple will result in a poor control signal and a slow current slew rate in case of load steps. a good starting point for peak to peak ripple is around 20 ? 40% of the inductor current at the maximum load at the worst case v in , but operation should be verified empirically. the worst case v in is half of v out , or whatever v in is closest to half of v in . after choosing a peak current ripple value, calculate the inductor value as follows: l v in(wc) 2 d wc i l,max f s v out where: v in(wc) : v in value as close as possible to half of v out [v] d wc : duty cycle at v in(wc) i l,max : maximum peak to peak ripple [a] the maximum average inductor current can be calculated as follows: i l,avg v out i out(max) v in(min) the peak inductor current can be calculated as follows: i l,peak i l,avg v in(min) 2 d wc l f s v out where: i l,peak : peak inductor current value [a]
NCV898031 http://onsemi.com 12 select output capacitors the output capacitors smooth the output voltage and reduce the overshoot and undershoot associated with line transients. the steady state output ripple associated with the output capacitors can be calculated as follows: v out(ripple) i out(max) (v out v in(wc) ) c out f
2 i out(max) v out r esr v in(wc) the capacitors need to survive an rms ripple current as follows: i cout(rms) i out v out v in(wc) v in(wc) the use of parallel ceramic bypass capacitors is strongly encouraged to help with the transient response. select input capacitors the input capacitor reduces voltage ripple on the input to the module associated with the ac component of the input current. i cin(rms) v in(wc) 2 d wc l f s v out 23 select feedback resistors the feedback resistors form a resistor divider from the output of the converter to ground, with a tap to the feedback pin. during regulation, the divided voltage will equal v ref . the lower feedback resistor can be chosen, and the upper feedback resistor value is calculated as follows: r upper r lower v out v ref
v ref the total feedback resistance (r upper + r lower ) should be in the range of 1 k ? 100 k . select compensator components current mode control method employed by the NCV898031 allows the use of a simple, type ii compensation to optimize the dynamic response according to system requirements. select mosfet(s) in order to ensure the gate drive voltage does not drop out the mosfet(s) chosen must not violate the following inequality: q g(total) i drv f s where: q g(total) : total gate charge of mosfet(s) [c] i drv : drive voltage current [a] f s : switching frequency [hz] the maximum rms current can be calculated as follows: i d(max) i out d wc d wc the maximum voltage across the mosfet will be the maximum output voltage, which is the higher of the maximum input voltage and the regulated output voltaged: v q(max) v out(wc) select diode the output diode rectifies the output current. the average current through diode will be equal to the output current: i d(avg) i out(max) additionally, the diode must block voltage equal to the higher of the output voltage and the maximum input voltage: v d(max) v out(max) the maximum power dissipation in the diode can be calculated as follows: p d v f (max) i out(max) where: p d : power dissipation in the diode [w] v f(max) : maximum forward voltage of the diode [v] low voltage operation if the input voltage drops below the uvlo or mosfet threshold voltage, another voltage may be used to power the device. simply connect the voltage you would like to boost to the inductor and connect the stable voltage to the vin pin of the device. in boost configuration, the output of the converter can be used to power the device. in some cases it may be desirable to connect 2 sources to vin pin, which can be accomplished simply by connecting each of the sources through a diode to the vin pin.
NCV898031 http://onsemi.com 13 package dimensions soic ? 8 nb case 751 ? 07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches
scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCV898031/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

▲Up To Search▲

Price & Availability of NCV898031

	To Download NCV898031 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .